The present invention relates generally to systems, and more particularly, to a buffer for use with a charge pump.
There has been a trend toward lowering the power requirements of personal computers and other electronic devices, including mobile electronic systems. In order to reduce power consumption, much of the integrated circuitry used in personal computers is being redesigned to run at lower voltage supply levels. For example, many components that were previously designed to work with a 5 volt supply have been redesigned to work with a 3.3 volt supply. Some newer products, and many in development, have even lower supply voltages, which, in many cases, may be below 2 volts. Scaling of process technology is a key factor for power supply reduction due to reliability.
While supply voltages are being reduced, higher voltages may continue to be used for some computer system features. For example, a flash electrically erasable programmable memory (EEPROM) may be used in some computer systems to store the basic input/output system (BIOS) or as a random access memory storage device in various electronic systems. Flash memory devices typically use a much higher voltage and higher internal power for programming and erasing data than can be provided directly by an external low voltage power supply.
For example, a negative gate erase technique may be used for some flash EEPROM arrays to reduce the amount of current, and thus, power, during an erase operation. The negative gate erase technique uses a large negative voltage (typically minus nine or ten volts) at the gate terminal of the memory deviced and Vcc at the source terminal.
To supply the desired negative voltage for a negative gate erase operation, a negative charge pump may be used. One type of negative charge pump is described in U.S. Pat. No. 5,532,915 to Pantelakis et al. and assigned to the assignee of the present invention.
The charge pump of Pantelakis has a drawback, however. At supply voltages below a given level, when p-type (also referred to as p-channel) transistors of Pantelakis are turned on, they may operate in a region in which the transistors experience a measurable threshold voltage drop. If the p-type transistors of Pantelakis are not xe2x80x9cfully turned onxe2x80x9d such that there is effectively no threshold voltage drop across them when they are operating, additional stages may be required to achieve the same pumped output voltage. Further, the current provided by the charge pump of Pantelakis will be reduced.
If the supply voltage drops below the threshold voltage of one or more of the p-channel transistors, one or more of the transistors may not even be turned on when desired. For example, if the threshold voltage of a series connected p-channel transistor is more than the gate source swing, which is equal to the external power supply, due to body effect, the transistor will not turn on adequately. In such a case, the negative pumped voltage may not be passed from one stage of the p-channel device to the next stage. In other words, below a given supply voltage, the negative charge pump of Pantelakis may not work.
A split clock buffer for providing clock signals to a negative charge pump is described. The split clock buffer receives a first phase and a second phase of the clock signal, pumps the voltage level of the first phase from a first voltage level to a second voltage level. Then, the buffer outputs the pumped first phase to a boot node of the negative charge pump, and outputs the second phase to a pump node of the negative charge pump.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.